1. Field of the Invention
The present invention relates to an organic light emitting display (OLED) and a method of manufacturing the OLED, and more particularly, to an OLED in which a transparent metal layer is formed on a metal layer to function as a wiring line terminal. The transparent metal layer in formed is such a way that an oxide layer is prevented from being generated on the wiring line terminal.
2. Description of the Related Technology
Various flat panel displays have been developed so as to have less weight and bulk than that of a Cathode Ray Tube (CRT). The class of flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), organic light emitting displays, etc. An organic light emitting display presents an image using organic light emitting diodes that generate light from the-recombination of electrons and holes. Such an organic light emitting display has advantages in that it has a high response speed, and operates in a low power consumption. Flat panel displays often incorporate thin film transistors (TFT) which control the operation of the organic light emitting diodes.
FIG. 1 is a cross-sectional view illustrating the structure of a conventional OLED.
Referring to FIG. 1, in the conventional OLED, a display unit (a) and a pad unit (b) are formed on a substrate 100.
An activation layer 112 having source/drain regions 110 and a channel region 111 is formed in the display unit (a).
A gate insulating layer 113 is formed on the substrate 100 covering at least the activation layer 112. A gate electrode 114 is formed on the gate insulating layer 113 over the channel region 111.
An interlayer insulating layer 115 is formed on the top surface of the substrate 100 covering the gate electrode 114. Source/drain contact holes are formed in the interlayer insulating layer 115 to expose the source/drain regions 110.
Source/drain electrodes 116 are formed in the display unit (a) region on the interlayer insulating layer 115 and are connected to the source/drain regions 110, respectively, through the source/drain contact holes. A wiring line terminal 117 is formed in the pad unit b on the interlayer insulating layer 115. The wiring line terminal 117 is electrically connected to one of the source/drain electrodes 116 of the display unit (a) to transmit data signals to the source/drain electrode 116.
A planarization insulating layer 118 is formed on the top surface of the substrate 100 covering the wiring line terminal 117. A via hole 119 that exposes one of the source/drain electrodes 116 and a pad contact hole 120 that exposes the wiring line terminal 117 are formed in the planarization insulating layer 118.
A first transparent metal layer 121, an Ag layer 122, and a second transparent metal layer 123 are sequentially formed on the planarization insulating layer 118. The first transparent metal layer 121, the Ag layer 122, and the second transparent metal layer 123 are patterned so that a pixel electrode 124 is formed on the planarization insulating layer 118 of the display unit. Similarly, a pad electrode 125 connected to the wiring line terminal 117 through the pad contact hole 120 is formed on the planarization insulating layer 118 of the pad unit (b). Therefore, the pixel electrode 124 is formed by laminating the first transparent metal layer 121, the Ag layer 122, and the second transparent metal layer 123. The pad electrode 125 is formed by sequentially laminating a third transparent metal layer 126, an Ag layer 127, and a fourth transparent metal layer 128. When in operation, the light emitted from an emission layer (not shown) formed on the pixel electrode 121 is reflected from the Ag layer 122 that is a reflection layer so that it is possible to realize a top surface emission OLED that emits light through the substrate 100. On the other hand, the first through fourth transparent metal layers 121, 123, 126, and 128 are formed from an optically transmissive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).
The pad electrode 125 is exposed so that it may be bonded to an external module. Electrical signals from the external module are input thereto and the electrode is therefore vulnerable to external contaminating agents such as moisture or oxygen. When a metal having a rough surface is used as the wiring line terminal 117, and the third transparent metal layer 126 is formed on the wiring line terminal 117 with a thickness of about 50 Å, the third transparent metal layer 126 becomes too thin in certain areas. In such circumstances, the surface of the third transparent metal layer 126 adjacent to the Ag layer 127 is not sufficiently planar to prevent voids at the interface. Because of the voids, during subsequent processing, corrosive agents can gain access to the Ag layer 127. As a result, the Ag layer 127 may corrode in such a way that, for example, its volume may increase causing wiring defects to occur.